Opcode
| Machine code |
|---|
| General concepts |
| Instructions |
In computing, an opcode (abbreviated from operation code)[1][2] is an enumerated value that specifies the operation to be performed. Opcodes are employed in hardware devices such as arithmetic logic units (ALUs), central processing units (CPUs), and software instruction sets. In ALUs, the opcode is directly applied to circuitry via an input signal bus. In contrast, in CPUs, the opcode is the portion of a machine language instruction that specifies the operation to be performed.
CPUs
[edit]Opcodes are found in the machine language instructions of CPUs as well as in some abstract computing machines. In CPUs, an opcode may be referred to as an instruction machine code,[3] instruction code,[4] instruction syllable,[5][6][7][8] instruction parcel, or opstring.[9][2] For any particular processor (which may be a general CPU or a more specialized processing unit), the opcodes are defined by the processor's instruction set architecture (ISA).[10] They can be described using an opcode table. The types of operations may include arithmetic, data copying, logical operations, program control, and special instructions (e.g., CPUID).[10]
In addition to the opcode, many instructions specify the data (known as operands) the operation will act upon, although some instructions may have implicit operands or none.[10] Some instruction sets have nearly uniform fields for opcode and operand specifiers, whereas others (e.g., x86 architecture) have a less uniform, variable-length structure.[10][11] Instruction sets can be extended through opcode prefixes, which add a subset of new instructions made up of existing opcodes following reserved byte sequences.[citation needed]
Sample opcode table
[edit]This table shows opcodes of a simple 8-bit microprocessor, the Intel 8008 from 1972.
Each opcode is 8 bits long. Each is shown as a binary pattern of ones and zeros in the Opcode column. Up to two additional fields may be embedded into the opcode. Some 3-bit fields are labeled DDD, SSS, CC, and ALU. The SSS (source) and DDD (destination) fields specify one of the eight possible 8008 registers or memory: A, B, C, D, E, H, L, or M. CC specifies a condition that will activate certain JMP, CAL, and RET instructions. ALU specifies one of a possible eight arithmetic logic unit functions to be performed during an instruction, specifically, add, add with carry, subtract, subtract with borrow, logical AND, logical XOR, logical OR, and compare. The X in some fields means that either a 1 or 0 can be inserted with no effect.
The fixed ones and zeros are combined with the parameter fields to build the 8-bit opcode. Additionally, the full instruction might require one or two additional bytes of operands. These are shown in the second major column of the table labeled Operands. If no operands are required, the column is filled with a dash (—).
Since the ones and zeros are difficult to remember, the Mnemonic column shows a short, easy to remember letter code that an assembly language programmer may use to invoke the required opcode.
The Description column shows the function performed by the microprocessor when it encounters a specific opcode.
| Opcode | Operands | Mnemonic | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | |||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | X | — | — | HLT | Halt | |
| 0 | 0 | DDD | 0 | 0 | 0 | — | — | INr | DDD ← DDD + 1 (except A and M) | |||
| 0 | 0 | DDD | 0 | 0 | 1 | — | — | DCr | DDD ← DDD - 1 (except A and M) | |||
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | — | — | RLC | A1-7 ← A0-6; A0 ← Cy ← A7 | |
| 0 | 0 | CC | 0 | 1 | 1 | — | — | Rcc (RET conditional) | If cc true, P ← (stack) | |||
| 0 | 0 | ALU | 1 | 0 | 0 | data | — | ADI ACI SUI SBI NDI XRI ORI CPI data | A ← A [ALU operation] data | |||
| 0 | 0 | N | 1 | 0 | 1 | — | — | RST n | (stack) ← P, P ← N x 8 | |||
| 0 | 0 | DDD | 1 | 1 | 0 | data | — | LrI data (Load r with immediate data) | DDD ← data | |||
| 0 | 0 | X | X | X | 1 | 1 | 1 | — | — | RET | P ← (stack) | |
| 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | — | — | RRC | A0-6 ← A1-7; A7 ← Cy ← A0 | |
| 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | — | — | RAL | A1-7 ← A0-6; Cy ← A7; A0 ← Cy | |
| 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | — | — | RAR | A0-6 ← A1-7; Cy ← A0; A7 ← Cy | |
| 0 | 1 | CC | 0 | 0 | 0 | addlo | addhi | Jcc add (JMP conditional) | If cc true, P ← add | |||
| 0 | 1 | 0 | 0 | port | 1 | — | — | INP port | A ← Port (ports 0-7 only) | |||
| 0 | 1 | port | 1 | — | — | OUT port | Port ← A (ports 8-31 only) | |||||
| 0 | 1 | CC | 0 | 1 | 0 | addlo | addhi | Ccc add (CAL conditional) | If cc true, (stack) ← P, P ← add | |||
| 0 | 1 | X | X | X | 1 | 0 | 0 | addlo | addhi | JMP add | P ← add | |
| 0 | 1 | X | X | X | 1 | 1 | 0 | addlo | addhi | CAL add | (stack) ← P, P ← add | |
| 1 | 0 | ALU | SSS | — | — | ADr ACr SUr SBr NDr XRr ORr CPr | A ← A [ALU operation] SSS | |||||
| 1 | 1 | DDD | SSS | — | — | Lds (Load d with s) | DDD ← SSS | |||||
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | — | — | HLT | Halt | |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | Mnemonic | Description | |
| SSS DDD | 2 | 1 | 0 | CC | ALU | |||||||
| A | 0 | 0 | 0 | FC, C false | ADr ADI (A ← A + arg) | |||||||
| B | 0 | 0 | 1 | FZ, Z false | ACr ACI (A ← A + arg + Cy) | |||||||
| C | 0 | 1 | 0 | FS, S false | SUr SUI (A ← A - arg) | |||||||
| D | 0 | 1 | 1 | FP, P odd | SBr SBI (A ← A - arg - Cy) | |||||||
| E | 1 | 0 | 0 | TC, C true | NDr NDI (A ← A ∧ arg) | |||||||
| H | 1 | 0 | 1 | TZ, Z true | XRr XRI (A ← A ⊻ arg) | |||||||
| L | 1 | 1 | 0 | TS, S true | ORr ORI (A ← A ∨ arg) | |||||||
| M | 1 | 1 | 1 | TP, P even | CPr CPI (A - arg) | |||||||
| SSS DDD | 2 | 1 | 0 | CC | ALU | |||||||
Software instruction sets
[edit]Opcodes can be found in so-called byte codes and other representations intended for a software interpreter rather than a hardware device. These software-based instruction sets often employ slightly higher-level data types and operations than most hardware counterparts but are nevertheless constructed along similar lines. Examples include the byte code found in Java class files, which are then interpreted by the Java Virtual Machine (JVM), the byte code used in GNU Emacs for compiled Lisp code, NET Common Intermediate Language (CIL), and many others.[12]
See also
[edit]
References
[edit]- ^ Barron, David William (1978) [1971, 1969]. "2.1. Symbolic instructions". Written at University of Southampton, Southampton, UK. In Floretin, J. John (ed.). Assemblers and Loaders. Computer Monographs (3 ed.). New York, USA: Elsevier North-Holland Inc. p. 7. ISBN 0-444-19462-2. LCCN 78-19961. (xii+100 pages)
- ^ a b Chiba, Shigeru (2007) [1999]. "Javassist, a Java-bytecode translator toolkit". Archived from the original on 2020-03-02. Retrieved 2016-05-27.
- ^ "Appendix B - Instruction Machine Codes" (PDF). MCS-4 Assembly Language Programming Manual - The INTELLEC 4 Microcomputer System Programming Manual (Preliminary ed.). Santa Clara, California, USA: Intel Corporation. December 1973. pp. B-1 – B-8. MCS-030-1273-1. Archived (PDF) from the original on 2020-03-01. Retrieved 2020-03-02.
- ^ Raphael, Howard A., ed. (November 1974). "The Functions Of A Computer: Instruction Register And Decoder" (PDF). MCS-40 User's Manual For Logic Designers. Santa Clara, California, USA: Intel Corporation. p. viii. Archived (PDF) from the original on 2020-03-03. Retrieved 2020-03-03.
[…] Each operation that the processor can perform is identified by a unique binary number known as an instruction code. […]
- ^ Jones, Douglas W. (June 1988). "A Minimal CISC". ACM SIGARCH Computer Architecture News. 16 (3). New York, USA: Association for Computing Machinery (ACM): 56–63. doi:10.1145/48675.48684. S2CID 17280173.
- ^ Domagała, Łukasz (2012). "7.1.4. Benchmark suite". Application of CLP to instruction modulo scheduling for VLIW processors. Gliwice, Poland: Jacek Skalmierski Computer Studio. pp. 80–83 [83]. ISBN 978-83-62652-42-6. Archived from the original on 2020-03-02. Retrieved 2016-05-28.
- ^ Smotherman, Mark (2016) [2013]. "Multiple Instruction Issue". School of Computing, Clemson University. Archived from the original on 2016-05-28. Retrieved 2016-05-28.
- ^ Jones, Douglas W. (2016) [2012]. "A Minimal CISC". Computer Architecture On-Line Collection. Iowa City, USA: The University of Iowa, Department of Computer Science. Archived from the original on 2020-03-02. Retrieved 2016-05-28.
- ^ Schulman, Andrew (2005-07-01). "Finding Binary Clones with Opstrings & Function Digests". Dr. Dobb's Journal. Part I. Vol. 30, no. 7. CMP Media LLC. pp. 69–73. ISSN 1044-789X. #374. Archived from the original on 2020-03-02. Retrieved 2020-03-02; Schulman, Andrew (2005-08-01). "Finding Binary Clones with Opstrings & Function Digests". Dr. Dobb's Journal. Part II. Vol. 30, no. 8. CMP Media LLC. pp. 56–61. ISSN 1044-789X. #375. Archived from the original on 2020-03-02. Retrieved 2016-05-28; Schulman, Andrew (2005-09-01). "Finding Binary Clones with Opstrings & Function Digests". CMP Media LLC. Part III. Vol. 30, no. 9. United Business Media. pp. 64–70. ISSN 1044-789X. #376. Archived from the original on 2020-03-02. Retrieved 2016-05-28.
- ^ a b c d Hennessy, John L.; Patterson, David A.; Asanović, Krste; Bakos, Jason D.; Colwell, Robert P.; Bhattacharjee, Abhishek; Conte, Thomas M.; Duato, José; Franklin, Diana; Goldberg, David; Jouppi, Norman P.; Li, Sheng; Muralimanohar, Naveen; Peterson, Gregory D.; Pinkston, Timothy M.; Ranganathan, Parthasarathy; Wood, David A.; Young, Cliff; Zaky, Amr (2017-11-23). Computer architecture: A quantitative approach (6 ed.). Cambridge, Massachusetts, USA: Morgan Kaufmann Publishers. ISBN 978-0-12811905-1. OCLC 983459758.
- ^ Mansfield, Richard (1983). "Introduction: Why Machine Language?". Machine Language For Beginners. Compute! Books (1 ed.). Greensboro, North Carolina, USA: COMPUTE! Publications, Inc., American Broadcasting Companies, Inc.; Small System Services, Inc. ISBN 0-942386-11-6. Archived from the original on 2008-02-13. Retrieved 2016-05-28.
- ^ "bytecode Definition". PC Magazine. PC Magazine Encyclopedia. Archived from the original on 2012-10-06. Retrieved 2015-10-10.